Variability-Aware Pruning of Approximate CMOS Logic

Approximate computing has in recent years emerged as an important approach for energy saving mechanisms. Approximate computing involves reducing the number of transistors in a circuit to reduce delay and increase power savings. The power savings are at the cost of reduced accuracy. In most Signal Processing cases it is not necessary for the digital circuit to produce a precise output, the field of approximate computing takes advantage of the reduced accuracy requirements to improve speed and power consumption. This paper reviews methods used to approximate circuits and their performance in real-life applications. We also look at the effects of Process Variation on Approximate circuits where we analyze the effect of Variability on the signal delay of the critical path in approximate circuits. Keywords—inexact arithmetic units, approximate computing, adder, variable accuracy, low power, mirror adder, adders, error distance, power consumption, process variation ,delay, power reduction